Test MP+dmb.sy+[fr-rf]-data-rfi-addr

AArch64 MP+dmb.sy+[fr-rf]-data-rfi-addr
"DMB.SYdWW Rfe FrLeave RfBack DpDatadW Rfi DpAddrdR Fre"
Cycle=Rfi DpAddrdR Fre DMB.SYdWW Rfe FrLeave RfBack DpDatadW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpDatadW [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe FrLeave RfBack DpDatadW Rfi DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X8=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2        |             ;
 MOV W2,#1   | ADD W3,W3,#1        |             ;
 STR W2,[X3] | STR W3,[X4]         |             ;
             | LDR W5,[X4]         |             ;
             | EOR W6,W5,W5        |             ;
             | LDR W7,[X8,W6,SXTW] |             ;
Observed
    z=1; y=1; x=1; 1:X7=1; 1:X5=1; 1:X2=0; 1:X0=2;
and z=1; y=1; x=1; 1:X7=0; 1:X5=1; 1:X2=0; 1:X0=2;
and z=1; y=2; x=1; 1:X7=1; 1:X5=1; 1:X2=0; 1:X0=1;
and z=1; y=1; x=1; 1:X7=1; 1:X5=1; 1:X2=0; 1:X0=1;